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current output/serial input, 16 - /14 - bit dacs data sheet ad5543 / ad5553 rev. f information fu rnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2002 C 2012 analog devices, inc. all rights reserved. features 16 -b it r esolution ad5543 14 -b it r esolution ad5553 1 lsb dnl 1 lsb inl low n oise : 12 nv/hz low p ower: i dd = 10 a 0.5 s s ettling t ime 4q m ultiplying r eference i nput 2 ma f ull -s cale current 20%, with v ref = 10 v built - in rfb f acilitates v olta ge c onversion 3-w ire i nterface ultracompact 8- lead msop and 8- lead soic p ackages applications automatic t est e quipment instrumentation digitally c ontrolled c alibration industrial c ontrol plcs general description the ad5543/ad5553 are precision 16 - /14 - bit , low power, current output, small form factor digital - to - analog converters (dac s) . they are designed to operate from a single 5 v supply with a 10 v multiplying reference. the applied external reference , v ref , determines the full - scale output current. an internal feedback resistor (r fb ) facilitates the r- 2r and temperature tracking for voltage conversion when combined with an external op amp. a serial - data interface offers hig h speed, 3 - wire microcontroller - compatible inputs using serial data in (sdi), cl ock (clk), and chip select ( cs ). the ad5543/ad5553 are packaged in ultracompact (3 mm 4.7 mm) 8- lead msop and 8- lead soic packages. functional block dia gram 16-bit/14-bit shift register dac register ad5543/ad5553 dac v dd v ref r fb i out cs clk sdi gnd control logic 16 or 14 16 or 14 02917-001 figure 1. code 1.0 4096 inl (lsb) 0.8 8152 12,288 16,384 20,480 24,575 28,672 32,768 36,864 40,960 45,056 49,152 53,248 57,344 61,440 65,536 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 02917-002 f igure 2 . integ ral n onlinearity 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 10k 100k 1m 10m 100m gain (db) frequency (hz) 02917-025 figure 3 . refe rence multiplying bandwidth
ad5543/ad5553 data sheet rev. f | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing diagrams .......................................................................... 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? circuit operation ............................................................................. 9 ? dac section .................................................................................. 9 ? serial data interface ....................................................................... 10 ? esd protection circuits............................................................. 10 ? pcb layout and power supply bypassing .............................. 10 ? applications information .............................................................. 11 ? stability ........................................................................................ 11 ? positive voltage output ............................................................. 11 ? bipolar output ............................................................................ 11 ? programmable current source ................................................ 12 ? reference selection .................................................................... 12 ? amplifier selection .................................................................... 12 ? evaluation board ............................................................................ 14 ? system development platform ................................................. 14 ? ad5543/ad5553 to sport interface .................................... 14 ? waveform generator ................................................................. 14 ? operating the evaluation board .............................................. 14 ? bill of materials ........................................................................... 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 20 ? revision history 1/12rev. e to rev. f added figure 15, renumbered sequentially ................................ 8 change to table 9 ........................................................................... 13 changes to figure 27 ...................................................................... 15 changes to figure 28 ...................................................................... 16 replaced figure 29, figure 30, and figure 31 ............................. 17 2/11rev. d to rev. e added evaluation board section ................................................. 14 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 4/10rev. c to rev. d changes to figure 3 .......................................................................... 1 changes to table 1 ............................................................................ 3 moved timing diagrams section .................................................. 4 moved table 4 ................................................................................... 6 delete figure 13; renumbered sequentially ................................. 8 changes to figure 14 ........................................................................ 8 changes to figure 18 ........................................................................ 9 moved table 5 and table 6 ............................................................ 10 added reference selection section and amplifier selection section .............................................................................................. 12 added table 7, table 8, and table 9; renumbered sequentially .............................................................. 13 10/09rev. b to rev. c updated outline dimensions ..................................................... 14 changes to ordering guide .......................................................... 15 7/09rev. a to rev. b updated format .................................................................. universal change to features section .............................................................. 1 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 2/03rev. 0 to rev. a changes to ordering guide ............................................................. 3 12/02revision 0: initial version
data sheet ad5543/ad5553 rev. f | page 3 of 20 spe cifications v dd = 5 v 10%, v ss = 0 v, i out = v irtual gnd, gnd = 0 v, v ref = 10 v, t a = f ull operating temperature range, unless otherwise noted. table 1. parameter symbol condition 5 v 10% unit static performance 1 re solution n 1 lsb = v ref /2 16 = 153 v when v ref = 10 v ( ad5543 ) 16 bits 1 lsb = v ref /2 14 = 610 v when v ref = 10 v (ad5553) 14 bits relative accuracy inl grade: ad5553c 1 lsb max grade: ad5543c 1 lsb max grade: ad5543b 2 lsb max differential n onlinearity dnl monotonic 1 lsb max output leakage current i out data = 0 x0 000, t a = 25c 10 na max data = 0 x0 000, t a = t a max imum 20 na max full - scale gain error g fse data = 0xffff 1/ 4 mv typ/max full - scale temp erature coefficient 2 tcv fs 1 ppm/ c typ reference input v ref range v ref ?15/+15 v min/max input resistance r ref 5 k typ 3 input capacitance 2 c ref 5 pf typ analog output output current i out data = 0x ffff for ad5543 2 ma typ d ata = 0x 3fff for ad5553 output capacitance 2 c out code d ependent 200 pf typ logic inputs and output logic input low voltage v il 0.8 v max logic input high voltage v ih 2.4 v min input leakage curren t i il 10 a max input capacitance 2 c il 10 pf max interface timing 2 , 4 se e figure 4 and figure 5 clock input frequency f clk 50 mhz clock width high t ch 10 ns min clock width low t cl 10 ns min cs to clock setup t css 0 ns min clock to cs hold t csh 10 ns min data setup t ds 5 ns min data hold t dh 10 ns min supply characteristics power supply range v dd range 4.5/5.5 v min/max positive supply current i dd logic i nputs = 0 v 10 a max power dissipation p diss logic i nputs = 0 v 0.055 mw max power supply sensitivity p ss v dd = 5% 0.006 %/% max
ad5543/ad5553 data sheet rev. f | page 4 of 20 parameter symbol condition 5 v 10% unit ac characteristics 4 output voltage settling time t s to 0.1% of full s cale, 0.5 s typ data = 0 x0 000 to 0x ffff to 0 x00 00 for ad5543 data = 0 x0 000 to 0x 3fff to 0 x0 000 for ad5553 reference multiplying b andwidth bw v ref = 100 mv rms , d ata = 0x ffff 6.6 mhz typ dac glitch impulse q v ref = 0 v, d ata = 0x 7fff to 0x 8000 for ad5543 7 nv -s ec feedthrough error v out /v ref da ta = 0 x0 000, v ref = 100 mv rms, same channel ?83 db digital feedthrough q c s = 1 and f clk = 1 mhz 7 nv -s ec total harmonic distortion thd v ref = 5 v p - p, d ata = 0x ffff, f = 1 khz ?103 db typ output spot noise voltage e n f = 1 khz, bw = 1 hz 12 nv/hz 1 all static performance tests (except i out ) are performed in a closed - loop system using an external precision op177 i- to - v co nverter amplifier. the ad5543 r fb terminal is tied to the amplifier output. the +in op amp is grounded , and the dac i out is tied to the ? in op amp. typical values represent average readings measured at 25 c. 2 these parameters are guaranteed by design and are not subject to production testing. 3 all ac characteristic tests are performed in a closed - loop system using an ad8038 i- to - v converter amplifier except for thd where an ad8065 was used . 4 all input control signals are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. timing diagrams sdi clk cs t csh t css t ds t dh t ch t cl d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 02917-016 figure 4 . ad5543 tim ing diagram t csh t css t ds t dh t ch t cl sdi clk cs d13 d12 d11 d10 d9 d8 d7 d6 d1 d0 02917-017 figure 5 . ad5553 timi ng diagram
data sheet ad5543/ad5553 rev. f | page 5 of 20 absolute maximum rat ings table 2. parameter rating v dd to gnd ? 0.3 v to +8 v v ref to gnd ? 18 v to +18 v logic inputs to gnd ? 0.3 v to +8 v v(i out ) to gnd ? 0.3 v to v dd + 0.3 v input current to any pin e xcept supplies 50 ma package power dissipation (t j max ? t a )/ ja thermal resistance , ja 8- lead surface mount (msop) 150c/w 8- lead surface mount (soic) 100c/w maximum juncti on temperature (t j max ) 150c operating temperature range model b and model c ? 40c to +85c storage temperature range ? 65c to +150c lead temperature r - 8, rm - 8 (vapor phase, 60 sec) 215c r - 8, rm - 8 (infrared, 15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5543/ad5553 data sheet rev. f | page 6 of 20 pin configuration and function descripti ons clk 1 sdi 2 r fb 3 v ref 4 cs 8 v dd 7 gnd 6 i out 5 ad5543/ ad5553 top view (not to scale) 02917-004 figure 6. pin conf iguration table 3 . pin function descriptions pin o. mnemonic description 1 clk clock input. positive - edge triggered, clocks data into shift register. 2 sdi serial register input. data loads directly into the shift register msb first. extra leading bits are ignored. 3 r fb internal matching feedback resistor. this pin c on nects to an external op amp for voltage output. 4 v ref dac reference input pin. establishes dac full - scale voltage. constant input resistance vs. code. 5 i out dac current output. t his pin connects to the inverting terminal of the external precision i -to - v op amp for voltage output. 6 gnd analog and digital ground . 7 v dd positive power supply input. specified range of operation at 5 v 10%. 8 cs chip sel ect. active low digital input. transfers shift - register data to dac register on rising edge. see table 4 for operation. table 4 . control- logic truth table cl cs serial shift registe r function dac register x h no effect latched + 1 l shift register data advanced one bit latched x 1 h no effect latched x 1 + 1 shift register data transferred to dac register new data loaded from serial register 1 + = positive lo gic transition; x = don't c are .
data sheet ad5543/ad5553 rev. f | page 7 of 20 typical performance characteristics code (decimal) 1.0 inl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 65,536 8192 16,384 57,344 49,152 40,960 32,768 24,576 02917-005 figure 7 . ad5543 integral nonlinearity error code (decimal) 1.0 0 65,536 8192 dnl (lsb) 16,384 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 57,344 49,152 40,960 32,768 24,576 02917-006 figure 8 . ad5543 differential nonline arity error code (decimal) 1.0 0 14,336 inl (lsb) 16,384 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 12,288 10,240 8192 6144 4096 2048 02917-007 figure 9 . ad5553 integral nonlinearity e rror dnl (lsb) code (decimal) 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 16,384 2048 4096 14,336 12,288 10,240 8192 6144 02917-008 figure 10 . ad5553 differential nonlinearity error supply voltage v dd (v) 1.5 1.0 ?1.5 0 1 2 4 linearity er r or (lsb) 6 8 0.5 0 ?0.5 ?1.0 inl dnl ge v ref = 2.5v t a = 2 5 c 02917-009 f igure 11 . linearity error vs. vd d logic input v ol t a ge v ih (v) 5 4 0 supp l y current i dd (ma) 3 2 1 0 0.5 1.0 5.0 v dd = 5v t a = 2 5 c 2.0 1.5 2.5 3.0 3.5 4.0 4.5 02917-010 figure 12 . supply current vs. logic input voltage
ad5543/ad5553 data sheet rev. f | page 8 of 20 clock fre q uency (hz) 3.0 2.5 0 100m 10k 100k supp l y current (ma) 1m 10m 2.0 1.5 1.0 0.5 02917-011 0xffff 0x0000 0x8000 0x5555 figure 13 . ad5543 s upply current vs. clock frequency fre q uency (hz) 90 80 30 10k psrr (db) 1m 70 60 50 40 20 10 0 1k 100 10 v dd = 5v 10% v ref = 10v 100k 02917-012 figure 14 . power supply rejection ratio (psrr) vs . frequency 20 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 20 15 10 5 power spectrum (db) frequency (khz) 02917-200 figure 15 . ad5543/ad5553 analog thd 5v a2 ?5v 67.72 s dl y 2v 136ns 02917-014 figure 16 . settling time ?3.65 ?3.70 ?3.75 ?3.80 ?3.85 ?3.90 ?3.95 ?4.05 ?4.00 ?20 ?10 0 10 20 30 40 v out (v) time (ns) 02917-026 figure 17 . midscale transition and digital feedthrough
data sheet ad5543/ad5553 rev. f | page 9 of 20 circuit operation the ad5543 /ad5553 contain 16- /14 - bit current output, dac s, serial input register s, and dac register s . both converters use a 3- wire serial data interface . dac section the dac architecture uses a current steering r - 2r ladder design. figure 18 shows the typical equivalent dac structure. the dac contains a matching feedback resistor for use with an external op amp (see figure 19 ). with rfb and iout terminals connected to the op amp out put and inve rting node , respectively , a precision vo ltage output is achieved as v out = ?v ref d /65,536 (ad5543) (1) v out = ?v ref d /16,384 (ad5553) (2) note that the output voltage polarity is the opposite of the v ref polarity for dc reference voltages. these dacs are designed to operate with either negative or positive reference voltages. the v dd power pin is only used by the internal logic to drive the on and off states of the dac switches. v ref v dd r fb i out r r r gnd 2r 2r 2r s1 s2 digital interface connections omitted for clarity; switches s1 and s2 are closed, v dd must be powered. 5k? r 02917-018 figure 18 . equivalent r- 2r dac cir cuit note that a matching switch is used in series with the internal 5 k feedback resistor. if users attempt to measure r fb , power must be applied to v dd to achieve continuity. 02917-019 r fb i out 1 gnd sclk sdin v ref v ref r1 sync ad5543/ ad5553 v dd v dd agnd c1 a1 r2 v out = 0 to ?v ref controller notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (4pf to 6pf) may be required if a1 is a high speed amplifier. figure 19 . voltage output configuration these dacs are also designed to accommodate ac reference input signals. the ad5543 accommodates input reference voltages in the range of ? 12 v to +12 v. the reference voltage inputs exhibit a constant nominal input resistance value of 5 k ? 30%. the dac output (i out ) is code dependent, producing various resistances and capacitances. external amplifier choice should take into account the variation in impedance generated by the ad5543 on the inverting input node of the amplifier . the feedback resistance, in parallel with the dac ladder resistance, dominates output voltage noise. to main tain good analo g performance, power supply bypassing of 0.01 f to 0.1 f ceramic or chip capacitors , in parallel with a 1 f tantalum capacitor , is recommended. due to degradation of psrr in frequency, users must avoid using switching power supplies.
ad5543/ad5553 data sheet rev. f | page 10 of 20 serial data interface the ad5543/ad5553 use a 3-wire ( cs , sdi, clk) serial data interface. new serial data is clocked into the serial input register in a 16-bit data-word format for the ad5543. the msb is loaded first. table 5 defines the 16 data-word bits. data is placed on the sdi pin and clocked into the register on the positive clock edge of clk, subject to the data setup-and-hold time requirements that are specified in the interface timing specifications. only the last 16 bits clocked into the serial register are interrogated when the cs pin is strobed to transfer the serial register data to the dac register. because most microcontrollers output serial data in 8- bit bytes, two data bytes can be written to the ad5543/ad5553. after loading the serial register, the rising edge of cs transfers the serial register data to the dac register; during this strobe, the clk should not be toggled. for the ad5553, with 16-bit clock cycles, the two lsbs are ignored. esd protection circuits all logic input pins contain back-biased esd protection zener diodes that are connected to ground (dgnd) and v dd , as shown in figure 20. v dd digital inputs dgnd 5k? 0 2917-020 figure 20. equivalent esd protection circuits pcb layout and power supply bypassing it is a good practice to employ compact, minimum lead length pcb layout design. the leads to the input should be as short as possible to minimize ir drop and stray inductance. it is also essential to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. table 5. ad5543 serial input register data format; data loaded msb-first format b15 (msb) b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (lsb) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 6. ad5553 serial input register data format; data loaded msb-first format b13 (msb) 1 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (lsb) d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 a full 16-bit data-word can be loaded i nto the ad5553 serial input register, but only the last 14 bits entered are transferred to the dac register when cs returns to logic high.
data sheet ad5543/ad5553 rev. f | page 11 of 20 applications information stability v dd v ref v ref v dd u2 u1 ad554 3/ ad5553 v o gnd i out r fb ad8628 c1 02917-021 figure 21 . optional c ompensation capacitor for gain peaking prevention in the i - to - v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible to each other , and proper pcb layout technique must be employed. because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gbp and there is excessive parasitic capacitance at the inverting node. an optional compensation capacitor , c1, can be added for stability , as shown in figure 21 . c1 shou ld be found empirically , but 20 pf is generally adequate for the compensation. positive voltage out put to achieve the positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the toleran ce errors of the resistors . to generate a negative reference, the reference can be level -s hift ed by an op amp such that the vout and gnd pins of the reference become the virtual ground and ? 2.5 v, respectively (see figure 22). v ref v dd u2 u1 ad554 3/ ad5553 v o gnd i out r fb 1/2ad862 8 1/2ad8620 v out v in gnd v+ v? +5v ?5v adr03 +5v ?2.5v u3 u4 c1 0v < v o < +2.5v 02917-022 figure 22 . posi tive voltage output configuration bipolar output the ad5543/ad5553 are inherently 2- quadrant multiplying da cs . that is, they can easily be set up for unipolar output operation. the full - scale output polarity is the inverse of the reference input voltage. in some applications, it may be necessary to generate the full 4- quadrant multiplying capability or a bipolar output swing , which is easily accomplished by using an additional u4 external amplifier configured as a summing amplifier (se e figure 23 ). i n this circuit, the second amplifier , u4, provides a gain of 2 that increases the output span magnitude to 5 v. biasing the external amplifier with a 2.5 v offset from the reference voltage results in a full 4- quadrant multiplying circuit. the transfer equ ation of t his circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code zero (v out = ? 2.5 v) to midscale (v out = 0 v) to full - scale (v out = +2.5 v). v out = (d / 32,768 ? 1) v ref (ad5543) (3) v out = (d / 16,384 ? 1) v ref (ad5553) (4) for the ad5543, the resistance tolerance becomes the dominant error of which users should be aware. v ref v dd u2 u1 ad5553 only v o gnd i out r fb 1/2ad8620 v out v in gnd adr03 u3 1/2ad8620 v+ v? +5v ?5v +5v u4 c1 ?2.5v < v o < +2.5v c2 r3 r1 10k ? 0.01% 5k ? 0.01% 10k? 0.01% +5v r2 02917-023 figure 23 . 4- quadrant multiplying application circuit
ad5543/ad5553 data sheet rev. f | page 12 of 20 programmable current source figure 24 shows a versatile v - i conversion circuit using an improved howla nd current p ump. in addition to the p recision current conversion it provides, this circuit enables a bidirectional cu rrent flow and high voltage compliance. this circuit can be used in 4 ma to 20 ma current transmitters with up to 500 of load . in figure 24 , it can be shown that if the resistor network is matched, the load current is ( ) d v r3 r1 r3 r2 i ref l + = / (5) r3 in theory can be made small to ach ieve the current needed within the u3 output current driving capability. this circuit is versatile such that ad8510 can deliver 20 ma in both directions and the voltage compliance approaches 15 v, which is limit ed mainly by the supply voltages of u3. however, users must pay attention to the compensation. without c1, it can be shown th at the output impedance becomes ( ) ( ) ( ) r3 r2 r1 r3 r2 r1 r2 r1 r3 r1 z o + ? + + = ' ' ' ' (6) if the resistors are perfectly matched, z o is infinite, which is desir able, and behaves as an ideal current source. on the other hand, if they are not matched, z o can be either positive or negative. negative can cause oscillation. as a result, c1 is needed to prevent the oscillation. for critical applications, c1 could be fo und empirically but typically falls in the range of a few picofarads ( pf ) . u2 u1 ad5543/ad5553 v l gnd i out r fb ad8628 ad8510 v+ v? v ref v ref load u3 v dd v ss i l v dd v dd c1 10pf r2' 15k? r3' 50? r3 50? r1' 150k? r2 15k? r1 150k? 02917-024 figure 24 . pr ogrammable current source with bidirectional current control and high voltage compliance capabilities reference selection when selecting a re ference for use with the ad55xx series of current output dacs, pay attention to the output voltage , temperature coefficient specification of the reference . choosing a precision reference with a low output temperature coefficient minimizes error sources. table 7 lists some of the references available from analog devices , inc., that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current - steering mode is an amplifier wi th low input bias currents and low input offset voltage. because of the code - dependent output resistance of the dac, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain between two adjacent d igital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, c an cause the dac to be nonmonotonic. the input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, r fb . common - mode rejection of the op amp is impo rtant in voltage - switching circuits because it produces a code - dependent error at the voltage output of the circuit. provided that the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. consequently, the s lew rate and settling time of a voltage - switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node (the voltage output node in this application) of the dac. this is done by using low input capacitance buffer amplifiers and careful board design. analog devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in table 8 and table 9 .
data sheet ad5543/ad5553 rev. f | page 13 of 20 table 7. suitable analog devices precision references part no. output voltage (v) initial tolerance (%) maximum temperature drift (ppm/c) i ss (ma) output noise (v p-p) package(s) adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-5, sc70-5 adr02 5.0 0.06 3 1 10 soic-8 adr02 5.0 0.06 9 1 10 tsot-5, sc70-5 adr03 2.5 0.1 3 1 6 soic-8 adr03 2.5 0.1 9 1 6 tsot-5, sc70-5 adr06 3.0 0.1 3 1 10 soic-8 adr06 3.0 0.1 9 1 10 tsot-5, sc70-5 adr420 2.048 0.05 3 0.5 1.75 soic-8, msop-8 adr421 2.50 0.04 3 0.5 1.75 soic-8, msop-8 adr423 3.00 0.04 3 0.5 2 soic-8, msop-8 adr425 5.00 0.04 3 0.5 3.4 soic-8, msop-8 adr431 2.500 0.04 3 0.8 3.5 soic-8, msop-8 adr435 5.000 0.04 3 0.8 8 soic-8, msop-8 adr391 2.5 0.16 9 0.12 5 tsot-5 adr395 5.0 0.10 9 0.12 8 tsot-5 table 8. suitable analog devices precision op amps part no. supply voltage (v) v os maximum (v) i b maximum (na) 0.1 hz to 10 hz noise (v p-p) supply current (a) package(s) op97 2 to 20 25 0.1 0.5 600 soic-8 , pdip-8 op1177 2.5 to 15 60 2 0.4 500 msop-8, soic-8 ad8675 5 to 18 75 2 0.1 2300 msop-8, soic-8 ad8671 5 to 15 75 12 0.077 3000 msop-8, soic-8 ada4004-1 5 to 15 125 90 0.1 2000 soic-8, sot-23-5 ad8603 1.8 to 5 50 0.001 2.3 40 tsot-5 ad8607 1.8 to 5 50 0.001 2.3 40 msop-8, soic-8 ad8605 2.7 to 5 65 0.001 2.3 1000 wlcsp-5, sot-23-5 ad8615 2.7 to 5 65 0.001 2.4 2000 tsot-5 ad8616 2.7 to 5 65 0.001 2.4 2000 msop-8, soic-8 table 9. suitable analog devices high speed op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package(s) ad8065 5 to 24 145 180 1500 0.006 soic-8, sot-23-5 ad8066 5 to 24 145 180 1500 0.006 soic-8, msop-8 ad8021 5 to 24 490 120 1000 10,500 soic-8, msop-8 ad8038 3 to 12 350 425 3000 750 soic-8, sc70-5 ada4899-1 5 to 12 600 310 35 100 lfcsp-8, soic-8 ad8057 3 to 12 325 1000 5000 500 sot-23-5, soic-8 ad8058 3 to 12 325 850 5000 500 soic-8, msop-8 ad8061 2.7 to 8 320 650 6000 350 sot-23-5, soic-8 ad8062 2.7 to 8 320 650 6000 350 soic-8, msop-8 ad9631 3 to 6 320 1300 10,000 7000 soic-8, pdip-8
ad5543/ad5553 data sheet rev. f | page 14 of 20 evaluation board the eval-ad5543/eval-ad5553 is used in conjunction with an sdp1z system development platform board available from analog devices, which is purchased separately from the evaluation board. the usb-to-spi communication to the ad5543 is completed using this blackfin-based development board. the software offers a waveform generator. system development platform the system development platform (sdp) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. the sdp board is based on the blackfin bf527 processor with usb connectivity to the pc through a usb 2.0 high speed port. for more information about this device, see the system development platform web page . ad5543/ad5553 to sport interface the analog devices sdp has one sport serial port. the sport interface is used to control the ad5543/ad5553, allowing clock frequencies up to 30 mhz. sport_tfs sport_tsclk sport_dto cs sclk sdin ad5543/ad5553 adsp-bf527 02917-124 figure 25. ad5543/ad5553 to sport interface waveform generator the evaluation board software offers a waveform generator to show every change introduced and transmitted to the output. operating the evaluation board the evaluation board requires 12 v and +5 v supplies. the +12 v v dd and v ss are used to power the output amplifier, while the +5 v is used to power the dac (v dd1 ). 02917-125 figure 26. evaluation board softwarewaveform generator
data sheet ad5543/ad5553 rev. f | page 15 of 20 02917-126 v o u t s c l k s d i n / c s a g n d + c 1 1 0 u f c 2 0 . 1 u f v r e f + c 8 1 0 u f c 9 0 . 1 u f c 1 0 0 . 1 u f j 3 c 3 5 . 6 p f v o u t 2 - 3 + 6 o p 4 v - 7 v + 8 d i s u 3 + c 4 1 0 u f c 5 0 . 1 u f + c 6 1 0 u f c 7 0 . 1 u f j 4 5 i o u t 3 r f b 6 a g n d 1 s c l k 2 s d i n 8 c s 7 v d d 4 v r e f u 1 2 + v i n 5 t r i m 6 v o u t 4 g n d u 2 a d r 4 3 5 j 1 - 1 j 1 - 5 j 1 - 4 j 1 - 3 j 1 - 2 l k 1 d v d d v d d v d d v s s v s s v d d d v d d s c l k s d i n / c s d g n d dac + vin for sdp op amp + reference supply ad5543_53 figu re 27 . sch ematic of ad5543/ad5553 evaluation board
ad5543/ad5553 data sheet rev. f | page 16 of 20 02917-127 vin: use this pin to power the sdp requires 4-7v 200ma vio: use to set io voltage max draw 20ma board id eeprom (24lc64) must be on i2c bus 0, address is at user discretion i2c bus 1 is common across both connectors on sdp - pull up resistors required bmode1: pull up with a 10k resistor to set sdp to boot from a spi flash on the daughter board (connected to blackfin gpio - use i2c_0 first) main i2c bus (connected to blackfin twi - pull up resistors not required) connector standard sdp parallel port sport spi i2c general input/output timers * * * * * * * * * * * * * *nc on blackfin sdp 120 nc 119 nc 118 gnd 117 gnd 116 vio(+3.3v) 115 gnd 114 par_d22 113 par_d20 112 par_d18 111 par_d16 110 par_d15 109 gnd 108 par_d12 107 par_d10 106 par_d8 105 par_d6 104 gnd 103 par_d4 102 par_d2 101 par_d0 100 par_wr 99 par_int 98 gnd 97 par_a2 96 par_a0 95 par_fs2 94 par_clk 93 gnd 92 sport_rsclk 91 sport_dr0 90 sport_rfs 89 sport_tfs 88 sport_dt0 87 sport_tsclk 86 gnd 85 spi_sel_a 84 spi_mosi 83 spi_miso 82 spi_clk 81 gnd 80 sda_0 79 scl_0 78 gpio1 77 gpio3 76 gpio5 75 gnd 74 gpio7 73 tmr_b 72 tmr_d 71 nc 70 nc 69 gnd 68 nc 67 nc 66 nc 65 nc 64 nc 63 gnd 62 uart_tx 61 bmode1 60 reset_in 59 uart_rx 58 gnd 57 nc 56 nc 55 nc 54 nc 53 nc 52 gnd 51 nc 50 nc 49 tmr_c 48 tmr_a 47 gpio6 46 gnd 45 gpio4 44 gpio2 43 gpio0 42 scl_1 41 sda_1 40 gnd 39 spi_sel1/spi_ss 38 spi_sel_c 37 spi_sel_b 36 gnd 35 sport_int 34 sport_dt3 33 sport_dt2 32 sport_dt1 31 sport_dr1 30 sport_dr2 29 sport_dr3 28 gnd 27 par_fs1 26 par_fs3 25 par_a1 24 par_a3 23 gnd 22 par_cs 21 par_rd 20 par_d1 19 par_d3 18 par_d5 17 gnd 16 par_d7 15 par_d9 14 par_d11 13 par_d13 12 par_d14 11 gnd 10 par_d17 9 par_d19 8 par_d21 7 par_d23 6 gnd 5 usb_vbus 4 gnd 3 gnd 2 nc 1 vin j2 1 a0 2 a1 3 a2 4 vss 8 vcc 7 wp 6 scl 5 sda u4 24lc64 usb_vbus 3.3v_bf sclk sdin /cs start 3.3v_bf status figure 28 . sc hematic of sdp interface
data sheet ad5543/ad5553 rev. f | page 17 of 20 02917-128 figure 29 . silkscreen component side view (top layer) 02917-129 figure 30 component side artwork 02917-130 figure 31 . solder side artwork
ad5543/ad5553 data sheet rev. f | page 18 of 20 bill of m aterials table 10 . name part description value pcb decal part description cs testpoint testpoint red testpoint agnd testpoint testpoint black testpoint c1 capacitor+ 10 f rtaj_a 10 v smd tantalum capacitor c2 capacitor 0.1 f c0603 50 v x7r ceramic capacitor c3 capacitor 5.6 pf c0603 multilayer ceramic capacitor c4 capacitor+ 10 f rtaj_b 16 v tantalum capac itor c5 capacitor 0.1 f c0603 50 v x7r ceramic capacitor c6 capacitor+ 10 f rtaj_b 16 v tantalum capacitor c7 capacitor 0.1 f c0603 50 v x7r ceramic capacitor c8 capacitor+ 10 f rtaj_b 16 v tantalum capacitor c9 capacitor 0.1 f c0603 50 v x7r cer amic capacitor c10 capacitor 0.1 f c0603 50 v x7r ceramic capacitor c11 capacitor 10 f c0805 10 v 10 f ceramic capacitor 10% x5r 0805 c12 capacitor 0.1 f c0603 50 v x7r ceramic capacitor gl1 ground link component link copper short j1 con \ power5 con \ power5 5- pin termin al block j2 sdp - standard - conn con - 120/fx8-120s -sv 120- way connector, 0.6 mm pitch, receptacle j3 smb smb straight pcb mount smb jack 50 j4 smb smb straight pcb mount smb jack 50 sclk testpoint testpoint red testpoint sdi n testpoint testpoint red testpoint u1 ad5543/ad5553 so8nb digital -to - analog converter u2 adr435 so8nb 5 v reference u3 ad8038 so8nb single op amp 8 - pin u4 24lc64 mso8 64k i2c serial eeprom msop8 usb_vbus testpoint testpoint black testpoint vou t testpoint testpoint red testpoint vref testpoint testpoint red testpoint x1 mthole - 3mm mthole - 3mm 3 mm npth hole x2 mthole - 3mm mthole - 3mm 3 mm npth hole
data sheet ad5543/ad5553 rev. f | page 19 of 20 outline dimensions compliant to jedec stand a rds mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0. 40 0.25 1.10 max 3.20 3.00 2.80 copla narit y 0. 10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 ident ifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 32 . 8 - lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in p arenthe ses) are rounded-off millimete r equiv alents for r eference onl y and are not appropria te for use in des ign. compliant t o jedec st andards ms-012-aa 012 407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.157 4) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 33 . 8 - lead standard small outline package [soic _n ] narrow body (r - 8) dimensions shown in millimeters and (inches)
ad5543/ad5553 data sheet rev. f | page 20 of 20 ordering guide model 1 , 2 inl (lsb) res (lsb) temp erature range package description package option branding ad5543crmz 1 16 ?40c to +85c 8- lead msop rm -8 dev ad5543crmz - reel7 1 16 ?40c to +85c 8 - lead msop rm - 8 dev ad5543br 2 16 ?40c to +85c 8- lead soic_n r -8 ad5543brz 2 16 ?40c to +85c 8- lead soic_n r -8 ad5543brm 2 16 ?40c to +85c 8- lead msop rm -8 dxb ad5543brm - reel7 2 16 ?40c to +85c 8- lead msop rm -8 dxb ad5543brmz 2 16 ?40c to +85c 8- lead msop rm -8 dxb# ad5543brmz - reel7 2 16 ?40c to +85c 8- lead msop rm -8 dxb# AD5553CRM 1 14 ?40c to +85c 8- lead msop rm -8 duc AD5553CRM - reel7 1 14 ?40c to +85c 8- lead msop rm -8 duc AD5553CRMz 1 14 ?40c to +85c 8- lead msop rm -8 duc# AD5553CRMz - reel7 1 14 ?40c to +85c 8- lead msop rm -8 duc# eval - ad5543sdz evaluation board 1 the ad55 43 contains 1040 transistors. the die size measures 55 mil 73 mil or 4,015 sq. mil. 2 z = rohs compliant part, # denotes rohs - compliant product may be top or bottom marked. ? 2002 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02917 - 0- 1/12(f)

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